Integrated circuit devices continue to increase in performance, density and speed, with increasing advances in integrated circuit design and manufacturing. For example, Dynamic Random Access Memory (DRAM) integrated circuit memory devices have continued to provide lower power, lower cost and higher bandwidth. High bandwidth is important in order to obtain high speed read and write operations of the memory device.
One important aspect of obtaining high bandwidth is controlling the system clock of the DRAM. In particular, a DRAM typically includes a circuit which converts an external system clock into an internal clock which is used throughout the integrated circuit. High speed, synchronous operation of the internal system clock is important because internal operations of the DRAM are generally synchronized to the internal clock. Thus, a faster internal clock generally allows faster operation of the DRAM device.
As an example, if the time consumed for generating the internal clock from the external clock is about two nanoseconds, the actual time for operating an internal circuit using the internal clock is also generally about two nanoseconds. In this scenario, address hold times may need to be at least four nanoseconds. Accordingly, the operational speed of an integrated circuit device, and in particular an integrated circuit memory device, is generally dependent upon the speed in which an internal clock may be synchronously generated, and the synchronization accuracy of the internal clock throughout the integrated circuit. High speed synchronous generation of an internal clock throughout an integrated circuit is therefore desirable.